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author | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:56:06 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:56:06 +0200 |
commit | 2d7866b6583f2888eb66cd75ca64737d4afa4d74 (patch) | |
tree | 14e9e353c98745bb1e70a7cc413a8ffa6b86e26f /testsuite | |
parent | 59fda76c701948c840c7e60d352ed8abb7699955 (diff) | |
download | ghdl-2d7866b6583f2888eb66cd75ca64737d4afa4d74.tar.gz ghdl-2d7866b6583f2888eb66cd75ca64737d4afa4d74.tar.bz2 ghdl-2d7866b6583f2888eb66cd75ca64737d4afa4d74.zip |
synth: add a test for idff.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/dff01/dff12.vhdl | 25 | ||||
-rw-r--r-- | testsuite/synth/dff01/tb_dff12.vhdl | 47 | ||||
-rwxr-xr-x | testsuite/synth/dff01/testsuite.sh | 3 |
3 files changed, 74 insertions, 1 deletions
diff --git a/testsuite/synth/dff01/dff12.vhdl b/testsuite/synth/dff01/dff12.vhdl new file mode 100644 index 000000000..f046dca95 --- /dev/null +++ b/testsuite/synth/dff01/dff12.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff12 is + port (q : out std_logic; + d : std_logic; + clk : std_logic; + rstn : std_logic); +end dff12; + +architecture behav of dff12 is + signal ff : std_logic := '1'; +begin + process (clk, rstn) is + begin + if rising_edge (clk) then + if rstn = '0' then + ff <= '0'; + else + ff <= d; + end if; + end if; + end process; + q <= ff; +end behav; diff --git a/testsuite/synth/dff01/tb_dff12.vhdl b/testsuite/synth/dff01/tb_dff12.vhdl new file mode 100644 index 000000000..936a830be --- /dev/null +++ b/testsuite/synth/dff01/tb_dff12.vhdl @@ -0,0 +1,47 @@ +entity tb_dff12 is +end tb_dff12; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_dff12 is + signal clk : std_logic; + signal rstn : std_logic; + signal din : std_logic; + signal dout : std_logic; +begin + dut: entity work.dff12 + port map ( + q => dout, + d => din, + clk => clk, + rstn => rstn); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + rstn <= '1'; + wait for 1 ns; + assert dout = '1' severity failure; + rstn <= '0'; + pulse; + assert dout = '0' severity failure; + rstn <= '1'; + din <= '1'; + pulse; + assert dout = '1' severity failure; + din <= '0'; + pulse; + assert dout = '0' severity failure; + din <= '1'; + pulse; + assert dout = '1' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh index 7f52a9acd..3c3bc22f2 100755 --- a/testsuite/synth/dff01/testsuite.sh +++ b/testsuite/synth/dff01/testsuite.sh @@ -2,7 +2,8 @@ . ../../testenv.sh -for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07 dff08 dff09 dff10 dff11; do +for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07 dff08 dff09 \ + dff10 dff11 dff12; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |