testsuite/synth: add a test for #2109

2 files changed, 28 insertions, 0 deletions

diff --git a/testsuite/synth/issue2109/bug.vhdl b/testsuite/synth/issue2109/bug.vhdl
new file mode 100644
index 000000000..c514c6f99
--- /dev/null
+++ b/testsuite/synth/issue2109/bug.vhdl
@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+generic(
+    tmp : std_ulogic_vector(0 downto 1) := ""
+);
+port(
+    val : out std_ulogic_vector(0 downto 1)
+);
+end entity;
+
+architecture rtl of bug is
+begin
+   val <= tmp;
+end architecture;
diff --git a/testsuite/synth/issue2109/testsuite.sh b/testsuite/synth/issue2109/testsuite.sh
new file mode 100755
index 000000000..1361b7a0a
--- /dev/null
+++ b/testsuite/synth/issue2109/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog bug.vhdl -e > syn_bug.v
+
+if grep val syn_bug.v; then
+  exit 1
+fi
+
+echo "Test successful"