From e5e2caa620846928bb85ccc5206375c2b7321a66 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 27 Jun 2022 07:50:01 +0200
Subject: testsuite/synth: add a test for #2109

---
 testsuite/synth/issue2109/bug.vhdl     | 17 +++++++++++++++++
 testsuite/synth/issue2109/testsuite.sh | 11 +++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 testsuite/synth/issue2109/bug.vhdl
 create mode 100755 testsuite/synth/issue2109/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue2109/bug.vhdl b/testsuite/synth/issue2109/bug.vhdl
new file mode 100644
index 000000000..c514c6f99
--- /dev/null
+++ b/testsuite/synth/issue2109/bug.vhdl
@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+generic(
+    tmp : std_ulogic_vector(0 downto 1) := ""
+);
+port(
+    val : out std_ulogic_vector(0 downto 1)
+);
+end entity;
+
+architecture rtl of bug is
+begin
+   val <= tmp;
+end architecture;
diff --git a/testsuite/synth/issue2109/testsuite.sh b/testsuite/synth/issue2109/testsuite.sh
new file mode 100755
index 000000000..1361b7a0a
--- /dev/null
+++ b/testsuite/synth/issue2109/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog bug.vhdl -e > syn_bug.v
+
+if grep val syn_bug.v; then
+  exit 1
+fi
+
+echo "Test successful"
-- 
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