testsuite/synth: add a test for #2093

3 files changed, 54 insertions, 1 deletions

diff --git a/testsuite/synth/issue2054/testcase2.vhdl b/testsuite/synth/issue2054/testcase2.vhdl
new file mode 100644
index 000000000..614c4f29a
--- /dev/null
+++ b/testsuite/synth/issue2054/testcase2.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+    port (
+        clk : in std_logic;
+        i   : in std_ulogic_vector(63 downto 0);
+        o   : out std_ulogic_vector(63 downto 0)
+        );
+end entity testcase;
+
+architecture behaviour of testcase is
+    signal edge : std_ulogic_vector(63 downto 0);
+begin
+    testcase_0: process(clk)
+    begin
+        if rising_edge(clk) then
+            edge <= i;
+            o <= edge;
+        end if;
+    end process;
+end behaviour;
diff --git a/testsuite/synth/issue2054/testcase3.vhdl b/testsuite/synth/issue2054/testcase3.vhdl
new file mode 100644
index 000000000..8323db17e
--- /dev/null
+++ b/testsuite/synth/issue2054/testcase3.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+    port (
+        clk : in std_logic;
+        i   : in std_ulogic_vector(63 downto 0);
+        o   : out std_ulogic_vector(63 downto 0)
+        );
+end entity testcase;
+
+architecture behaviour of testcase is
+    signal edge : std_ulogic_vector(63 downto 0) := (others => '1');
+begin
+    testcase_0: process(clk)
+    begin
+        if rising_edge(clk) then
+            edge <= i;
+            o <= edge;
+        end if;
+    end process;
+end behaviour;
diff --git a/testsuite/synth/issue2054/testsuite.sh b/testsuite/synth/issue2054/testsuite.sh
index af0825e54..a51e970f4 100755
--- a/testsuite/synth/issue2054/testsuite.sh
+++ b/testsuite/synth/issue2054/testsuite.sh
@@ -3,9 +3,18 @@
 . ../../testenv.sh
 
 synth --out=verilog flip_flop.vhdl -e > syn_flip_flop.v
-
 if grep "input  wire" syn_flip_flop.v; then
   exit 1
 fi
 
+synth --out=verilog testcase2.vhdl -e > syn_testcase2.v
+if grep "assign edge" syn_testcase2.v; then
+  exit 1
+fi
+
+synth --out=verilog testcase3.vhdl -e > syn_testcase3.v
+if grep "edge =" syn_testcase3.v; then
+  exit 1
+fi
+
 echo "Test successful"