1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/issue2054/testcase3.vhdl b/testsuite/synth/issue2054/testcase3.vhdl
new file mode 100644
index 000000000..8323db17e
--- /dev/null
+++ b/testsuite/synth/issue2054/testcase3.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+    port (
+        clk : in std_logic;
+        i   : in std_ulogic_vector(63 downto 0);
+        o   : out std_ulogic_vector(63 downto 0)
+        );
+end entity testcase;
+
+architecture behaviour of testcase is
+    signal edge : std_ulogic_vector(63 downto 0) := (others => '1');
+begin
+    testcase_0: process(clk)
+    begin
+        if rising_edge(clk) then
+            edge <= i;
+            o <= edge;
+        end if;
+    end process;
+end behaviour;