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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-09 05:34:37 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-09 05:34:37 +0200 |
| commit | 7064ef37029a883d0098d0af665231b36854d5e2 (patch) | |
| tree | 68af75d817e94da8fb20d654ae8d97302da9627e /testsuite/synth | |
| parent | 33740eb403c9dfbe3fc1f75b50de3000535da6bc (diff) | |
| download | ghdl-7064ef37029a883d0098d0af665231b36854d5e2.tar.gz ghdl-7064ef37029a883d0098d0af665231b36854d5e2.tar.bz2 ghdl-7064ef37029a883d0098d0af665231b36854d5e2.zip | |
testsuite/synth: add a test for #2084
Diffstat (limited to 'testsuite/synth')
| -rw-r--r-- | testsuite/synth/issue2084/bug.vhdl | 15 | ||||
| -rwxr-xr-x | testsuite/synth/issue2084/testsuite.sh | 8 |
2 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue2084/bug.vhdl b/testsuite/synth/issue2084/bug.vhdl new file mode 100644 index 000000000..847ac0f1b --- /dev/null +++ b/testsuite/synth/issue2084/bug.vhdl @@ -0,0 +1,15 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is + port ( + src : in std_ulogic_vector(31 downto 0) + ); +end bug; + +architecture rtl of bug is + type array_t is array(0 to 0) of src'subtype; + signal s : array_t; +begin + +end architecture; diff --git a/testsuite/synth/issue2084/testsuite.sh b/testsuite/synth/issue2084/testsuite.sh new file mode 100755 index 000000000..c355095b7 --- /dev/null +++ b/testsuite/synth/issue2084/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only bug + +echo "Test successful" |