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author | Tristan Gingold <tgingold@free.fr> | 2023-04-23 09:50:39 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-04-23 09:50:39 +0200 |
commit | 48f0f7c1addb5ced1e0da1892cfaf3c97ef10781 (patch) | |
tree | fba0b929911aee95004c46efebee284c1efac377 /testsuite/synth | |
parent | 71a9d2d734ba1f613ae37fca73c19854751fe5f2 (diff) | |
download | ghdl-48f0f7c1addb5ced1e0da1892cfaf3c97ef10781.tar.gz ghdl-48f0f7c1addb5ced1e0da1892cfaf3c97ef10781.tar.bz2 ghdl-48f0f7c1addb5ced1e0da1892cfaf3c97ef10781.zip |
testsuite/synth: add a test for previous commit
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/external01/externalerr02.vhdl | 65 | ||||
-rwxr-xr-x | testsuite/synth/external01/testsuite.sh | 1 |
2 files changed, 66 insertions, 0 deletions
diff --git a/testsuite/synth/external01/externalerr02.vhdl b/testsuite/synth/external01/externalerr02.vhdl new file mode 100644 index 000000000..42af5d5f7 --- /dev/null +++ b/testsuite/synth/external01/externalerr02.vhdl @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity externalerr02_sub is + port (clk : std_logic; + rst : std_logic; + a : std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0)); +end externalerr02_sub; + +architecture behav of externalerr02_sub is + signal accum : std_logic_vector(7 downto 0); +begin + process (clk) is + begin + if rising_edge(clk) then + if rst = '1' then + accum <= (others => '0'); + else + accum <= std_logic_vector(unsigned(accum) + unsigned(a)); + end if; + end if; + end process; + + process (clk) is + begin + if rising_edge(clk) then + if rst = '1' then + o <= (others => '0'); + else + o <= accum; + end if; + end if; + end process; +end behav; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity externalerr02 is + port (clk : std_logic; + rst : std_logic; + a : std_logic_vector(7 downto 0); + accum : out std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0)); +end externalerr02; + +architecture behav of externalerr02 is + component externalerr02_sub is + port ( + clk : std_logic; + rst : std_logic; + a : std_logic_vector(7 downto 0); + o : out std_logic_vector(7 downto 0)); + end component externalerr02_sub; +begin + dut : entity externalerr02_sub + port map (clk => clk, + rst => rst, + a => a, + o => o); + accum <= << signal .externalerr02.dut.accum : std_logic_vector(7 downto 0) >>; +end behav; diff --git a/testsuite/synth/external01/testsuite.sh b/testsuite/synth/external01/testsuite.sh index 1b3dfc367..12ca0c07a 100755 --- a/testsuite/synth/external01/testsuite.sh +++ b/testsuite/synth/external01/testsuite.sh @@ -8,5 +8,6 @@ GHDL_SYNTH_FLAGS=--keep-hierarchy=no synth_only external01 synth_failure externalerr01.vhdl -e +synth_failure externalerr02.vhdl -e echo "Test successful" |