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authorTristan Gingold <tgingold@free.fr>2020-03-22 08:24:54 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-22 08:25:18 +0100
commit8a35846d7e91f26d22cb059cfbf21d9e5645314d (patch)
tree342f6a8e2730c9f6a3997a505a6d848d0da45c49 /testsuite/synth/synth93
parent283a032e58d32a72873c647e017da3760bdedb53 (diff)
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testsuite/synth: add tests for previous commit.
Diffstat (limited to 'testsuite/synth/synth93')
-rw-r--r--testsuite/synth/synth93/a.vhdl28
-rwxr-xr-xtestsuite/synth/synth93/testsuite.sh8
2 files changed, 36 insertions, 0 deletions
diff --git a/testsuite/synth/synth93/a.vhdl b/testsuite/synth/synth93/a.vhdl
new file mode 100644
index 000000000..0b2b5b6b2
--- /dev/null
+++ b/testsuite/synth/synth93/a.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+
+entity A is
+ port (
+ clk : in std_logic;
+ input : in std_logic;
+ output : out std_logic
+ );
+
+end entity A;
+
+
+architecture RTL of A is
+begin
+
+ not_proc : process (clk)
+
+ variable not_input : std_logic := '0';
+
+ begin
+ if rising_edge(clk) then
+ not_input := not input;
+ end if;
+
+ output <= not_input;
+ end process;
+end RTL;
diff --git a/testsuite/synth/synth93/testsuite.sh b/testsuite/synth/synth93/testsuite.sh
new file mode 100755
index 000000000..f5bc3653e
--- /dev/null
+++ b/testsuite/synth/synth93/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze a
+clean
+
+echo "Test successful"