1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/synth93/a.vhdl b/testsuite/synth/synth93/a.vhdl
new file mode 100644
index 000000000..0b2b5b6b2
--- /dev/null
+++ b/testsuite/synth/synth93/a.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+
+entity A is
+  port (
+    clk : in std_logic;
+        input : in std_logic;
+        output : out std_logic
+    );
+
+end entity A;
+
+
+architecture RTL of A is
+begin
+
+    not_proc : process (clk)
+
+        variable not_input : std_logic := '0';
+
+    begin
+        if rising_edge(clk) then
+      not_input := not input;
+    end if;
+
+    output <= not_input;
+    end process;
+end RTL;