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author | Tristan Gingold <tgingold@free.fr> | 2019-10-15 07:34:09 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-15 07:34:09 +0200 |
commit | 81d4bd7833d5d295ced6f51b507b0102e515da60 (patch) | |
tree | bac880e84d4d0823dc82f7db639b0c8c85d91d08 /testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl | |
parent | d70fe587b2fd10eb8fca337af553a2a65aa434a8 (diff) | |
download | ghdl-81d4bd7833d5d295ced6f51b507b0102e515da60.tar.gz ghdl-81d4bd7833d5d295ced6f51b507b0102e515da60.tar.bz2 ghdl-81d4bd7833d5d295ced6f51b507b0102e515da60.zip |
testsuite/synth: add testcase for previous commit.
Diffstat (limited to 'testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl')
-rw-r--r-- | testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl b/testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl new file mode 100644 index 000000000..d7391da97 --- /dev/null +++ b/testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl @@ -0,0 +1,18 @@ +architecture rtl_comp_inst of leds_wrapper is + +begin + + leds_comp_inst : entity work.leds(spin1) + port map( + clk => clk, + led1 => led1, + led2 => led2, + led3 => led3, + led4 => led4, + led5 => led5, + led6 => led6, + led7 => led7, + led8 => led8 + ); + +end architecture; |