testsuite/synth: add testcase for previous commit.

6 files changed, 118 insertions, 0 deletions

diff --git a/testsuite/synth/synth60/leds.vhdl b/testsuite/synth/synth60/leds.vhdl
new file mode 100644
index 000000000..557585b7c
--- /dev/null
+++ b/testsuite/synth/synth60/leds.vhdl
@@ -0,0 +1,8 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity leds is
+  port (clk : in std_logic;
+        led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic);
+end leds;
diff --git a/testsuite/synth/synth60/leds_wrapper.vhdl b/testsuite/synth/synth60/leds_wrapper.vhdl
new file mode 100644
index 000000000..ff351d343
--- /dev/null
+++ b/testsuite/synth/synth60/leds_wrapper.vhdl
@@ -0,0 +1,8 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity leds_wrapper is
+  port (clk : in std_logic;
+        led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic);
+end leds_wrapper;
diff --git a/testsuite/synth/synth60/leds_wrapper_arch_comp_inst.vhdl b/testsuite/synth/synth60/leds_wrapper_arch_comp_inst.vhdl
new file mode 100644
index 000000000..98b6c75a8
--- /dev/null
+++ b/testsuite/synth/synth60/leds_wrapper_arch_comp_inst.vhdl
@@ -0,0 +1,23 @@
+architecture rtl_comp_inst of leds_wrapper is
+
+  component leds is
+    port (clk : in std_logic;
+          led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic);
+  end component;
+
+begin
+
+  leds_comp_inst : leds
+    port map(
+      clk => clk,
+      led1 => led1,
+      led2 => led2,
+      led3 => led3,
+      led4 => led4,
+      led5 => led5,
+      led6 => led6,
+      led7 => led7,
+      led8 => led8
+    );
+
+end architecture;
diff --git a/testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl b/testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl
new file mode 100644
index 000000000..d7391da97
--- /dev/null
+++ b/testsuite/synth/synth60/leds_wrapper_arch_entity_inst.vhdl
@@ -0,0 +1,18 @@
+architecture rtl_comp_inst of leds_wrapper is
+
+begin
+
+  leds_comp_inst : entity work.leds(spin1)
+    port map(
+      clk => clk,
+      led1 => led1,
+      led2 => led2,
+      led3 => led3,
+      led4 => led4,
+      led5 => led5,
+      led6 => led6,
+      led7 => led7,
+      led8 => led8
+    );
+
+end architecture;
diff --git a/testsuite/synth/synth60/spin1.vhdl b/testsuite/synth/synth60/spin1.vhdl
new file mode 100644
index 000000000..7c505869c
--- /dev/null
+++ b/testsuite/synth/synth60/spin1.vhdl
@@ -0,0 +1,54 @@
+architecture spin1 of leds is
+  signal nrst : std_logic := '0';
+  signal clk_4hz: std_logic;
+  signal leds : std_ulogic_vector (1 to 5);
+begin
+  (led1, led2, led3, led4, led5) <= leds;
+  led6 <= '0';
+  led7 <= '0';
+  led8 <= '0';
+
+  process (clk)
+    variable cnt : unsigned (1 downto 0) := "00";
+  begin
+    if rising_edge (clk) then
+      if cnt = 3 then
+        nrst <= '1';
+      else
+        cnt := cnt + 1;
+      end if;
+    end if;
+  end process;
+
+  process (clk)
+    --  3_000_000 is 0x2dc6c0
+    variable counter : unsigned (23 downto 0);
+  begin
+    if rising_edge(clk) then
+      if nrst = '0' then
+        counter := x"000000";
+      else
+        if counter = 2_999_999 then
+          counter := x"000000";
+          clk_4hz <= '1';
+        else
+          counter := counter + 1;
+          clk_4hz <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if nrst = '0' then
+        -- Initialize
+        leds <= "11000";
+      elsif clk_4hz = '1' then
+        --  Rotate
+        leds <= (leds (4), leds (1), leds (2), leds (3), '0');
+      end if;
+    end if;
+  end process;
+end spin1;
diff --git a/testsuite/synth/synth60/testsuite.sh b/testsuite/synth/synth60/testsuite.sh
new file mode 100755
index 000000000..54d500967
--- /dev/null
+++ b/testsuite/synth/synth60/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth leds.vhdl spin1.vhdl leds_wrapper.vhdl leds_wrapper_arch_entity_inst.vhdl -e > syn_leds.vhdl
+
+echo "Test successful"