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author | Tristan Gingold <tgingold@free.fr> | 2020-05-09 18:32:41 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-09 18:32:41 +0200 |
commit | 06202188e0e88c0096518415413c08bd0471644b (patch) | |
tree | 088ba5316602b01c9d2cedbfc6f6b37952b4b521 /testsuite/synth/synth104/case02.vhdl | |
parent | 894bbd7c174bafd59fbea3b3bd990ffdfbb685d2 (diff) | |
download | ghdl-06202188e0e88c0096518415413c08bd0471644b.tar.gz ghdl-06202188e0e88c0096518415413c08bd0471644b.tar.bz2 ghdl-06202188e0e88c0096518415413c08bd0471644b.zip |
testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#104
Diffstat (limited to 'testsuite/synth/synth104/case02.vhdl')
-rw-r--r-- | testsuite/synth/synth104/case02.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/synth104/case02.vhdl b/testsuite/synth/synth104/case02.vhdl new file mode 100644 index 000000000..f2a0ec3cb --- /dev/null +++ b/testsuite/synth/synth104/case02.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity case02 is + port ( + sel : in unsigned(3 downto 0); + det : out std_logic_vector(1 downto 0) + ); +end case02; + +architecture behavior of case02 is +begin + tc: process(sel) + begin + case to_integer(sel) is + when 0 to 1 => + det <= "00"; + when 2 | 7 downto 4 => + det <= "01"; + when 3 | 12 downto 10 | 8 to 9 => + det <= "10"; + when others => + det <= "11"; + end case; + end process; +end behavior; |