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author | Tristan Gingold <tgingold@free.fr> | 2019-09-15 06:32:47 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-15 06:32:47 +0200 |
commit | 251587405f6f760f069f1a3624296b7cb933b38e (patch) | |
tree | 9b6c13eb54c0a62f129e1f04f15b9c4dc1fe646b /testsuite/synth/oper01/tb_match01.vhdl | |
parent | 8b9310deab06d428050153eec5abd33bfb717584 (diff) | |
download | ghdl-251587405f6f760f069f1a3624296b7cb933b38e.tar.gz ghdl-251587405f6f760f069f1a3624296b7cb933b38e.tar.bz2 ghdl-251587405f6f760f069f1a3624296b7cb933b38e.zip |
testsuite/synth: add a test for std_match
Diffstat (limited to 'testsuite/synth/oper01/tb_match01.vhdl')
-rw-r--r-- | testsuite/synth/oper01/tb_match01.vhdl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/synth/oper01/tb_match01.vhdl b/testsuite/synth/oper01/tb_match01.vhdl new file mode 100644 index 000000000..e7c1a2b53 --- /dev/null +++ b/testsuite/synth/oper01/tb_match01.vhdl @@ -0,0 +1,30 @@ +entity tb_match01 is +end tb_match01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_match01 is + signal l : std_ulogic_vector(11 downto 0); + signal r : boolean; +begin + match01_1: entity work.match01 + port map (l, r); + + process + begin + l <= x"f00"; + wait for 1 ns; + assert r severity failure; + + l <= x"ff0"; + wait for 1 ns; + assert r severity failure; + + l <= x"ef0"; + wait for 1 ns; + assert not r severity failure; + + wait; + end process; +end behav; |