From 251587405f6f760f069f1a3624296b7cb933b38e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 15 Sep 2019 06:32:47 +0200
Subject: testsuite/synth: add a test for std_match

---
 testsuite/synth/oper01/tb_match01.vhdl | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 testsuite/synth/oper01/tb_match01.vhdl

(limited to 'testsuite/synth/oper01/tb_match01.vhdl')

diff --git a/testsuite/synth/oper01/tb_match01.vhdl b/testsuite/synth/oper01/tb_match01.vhdl
new file mode 100644
index 000000000..e7c1a2b53
--- /dev/null
+++ b/testsuite/synth/oper01/tb_match01.vhdl
@@ -0,0 +1,30 @@
+entity tb_match01 is
+end tb_match01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_match01 is
+  signal l  : std_ulogic_vector(11 downto 0);
+  signal r  : boolean;
+begin
+  match01_1: entity work.match01
+    port map (l, r);
+
+  process
+  begin
+    l <= x"f00";
+    wait for 1 ns;
+    assert r severity failure;
+
+    l <= x"ff0";
+    wait for 1 ns;
+    assert r severity failure;
+
+    l <= x"ef0";
+    wait for 1 ns;
+    assert not r severity failure;
+
+    wait;
+  end process;
+end behav;
-- 
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