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| author | Tristan Gingold <tgingold@free.fr> | 2021-06-21 07:43:55 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-06-21 08:07:13 +0200 |
| commit | 09e1764ea6dcf08aa77f8b6f5115caca9de44057 (patch) | |
| tree | c66014ebe875cad6ed20c6b7de326dab30b16286 /testsuite/synth/mem2d01/dpram2r.vhdl | |
| parent | 6aaabbfc1716fffd7b7185d53e791e77400950d2 (diff) | |
| download | ghdl-09e1764ea6dcf08aa77f8b6f5115caca9de44057.tar.gz ghdl-09e1764ea6dcf08aa77f8b6f5115caca9de44057.tar.bz2 ghdl-09e1764ea6dcf08aa77f8b6f5115caca9de44057.zip | |
testsuite/synth: check ram in mem01 and mem02
Diffstat (limited to 'testsuite/synth/mem2d01/dpram2r.vhdl')
| -rw-r--r-- | testsuite/synth/mem2d01/dpram2r.vhdl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/testsuite/synth/mem2d01/dpram2r.vhdl b/testsuite/synth/mem2d01/dpram2r.vhdl index 4419d5086..0b3c4646a 100644 --- a/testsuite/synth/mem2d01/dpram2r.vhdl +++ b/testsuite/synth/mem2d01/dpram2r.vhdl @@ -18,6 +18,7 @@ begin process (clk) begin if rising_edge (clk) then + -- Not a memory: different widths rdat <= mem (raddr)(rnib * 4 + 3 downto rnib * 4); mem (waddr) <= wdat; end if; |