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author | Tristan Gingold <tgingold@free.fr> | 2019-10-03 19:53:02 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-03 19:53:02 +0200 |
commit | a94d2a0592495f3216c54b63e9591d6af760d999 (patch) | |
tree | 7209f3a6d8ba65c3813bc3969c5ed46c2bd78b5c /testsuite/synth/issue963/tb_ent2.vhdl | |
parent | e5db9a577de24275c1911fc2ad09ab14db39e106 (diff) | |
download | ghdl-a94d2a0592495f3216c54b63e9591d6af760d999.tar.gz ghdl-a94d2a0592495f3216c54b63e9591d6af760d999.tar.bz2 ghdl-a94d2a0592495f3216c54b63e9591d6af760d999.zip |
testsuite/synth: add a test for FF inference.
Diffstat (limited to 'testsuite/synth/issue963/tb_ent2.vhdl')
-rw-r--r-- | testsuite/synth/issue963/tb_ent2.vhdl | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/testsuite/synth/issue963/tb_ent2.vhdl b/testsuite/synth/issue963/tb_ent2.vhdl new file mode 100644 index 000000000..daf1865cb --- /dev/null +++ b/testsuite/synth/issue963/tb_ent2.vhdl @@ -0,0 +1,98 @@ +entity tb_ent2 is +end tb_ent2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent2 is + signal clk : std_logic; + signal dout : std_logic_vector(3 downto 0); + signal set_0 : std_logic; + signal set_a : std_logic; + signal set_f : std_logic; + signal set_7 : std_logic; +begin + dut: entity work.ent2 + port map ( + set_0 => set_0, + set_a => set_a, + set_f => set_f, + set_7 => set_7, + q => dout, + clk => clk); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + set_0 <= '1'; + set_a <= '0'; + set_f <= '0'; + set_7 <= '0'; + pulse; + assert dout = x"0" severity failure; + + set_0 <= '0'; + set_a <= '0'; + set_f <= '0'; + set_7 <= '0'; + pulse; + assert dout = x"1" severity failure; + + set_0 <= '0'; + set_a <= '0'; + set_f <= '0'; + set_7 <= '0'; + pulse; + assert dout = x"2" severity failure; + + set_0 <= '0'; + set_a <= '1'; + set_f <= '0'; + set_7 <= '0'; + pulse; + assert dout = x"a" severity failure; + + set_0 <= '0'; + set_a <= '0'; + set_f <= '0'; + set_7 <= '0'; + pulse; + assert dout = x"b" severity failure; + + set_0 <= '0'; + set_a <= '0'; + set_f <= '1'; + set_7 <= '0'; + pulse; + assert dout = x"f" severity failure; + + set_0 <= '0'; + set_a <= '0'; + set_f <= '0'; + set_7 <= '1'; + pulse; + assert dout = x"7" severity failure; + + set_0 <= '1'; + set_a <= '0'; + set_f <= '0'; + set_7 <= '1'; + pulse; + assert dout = x"0" severity failure; + + set_0 <= '0'; + set_a <= '1'; + set_f <= '0'; + set_7 <= '1'; + pulse; + assert dout = x"a" severity failure; + + wait; + end process; +end behav; |