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author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 21:04:55 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 21:04:55 +0200 |
commit | bb00cae25caff518b54c28ba8cc6ee7381fdf2ac (patch) | |
tree | 9f7afea27413c5f22105b932d471c3cc3c2e7109 /testsuite/synth/issue956/ent.vhdl | |
parent | 21e59e89b5437ae0f3715b3f84f47f446e91d52d (diff) | |
download | ghdl-bb00cae25caff518b54c28ba8cc6ee7381fdf2ac.tar.gz ghdl-bb00cae25caff518b54c28ba8cc6ee7381fdf2ac.tar.bz2 ghdl-bb00cae25caff518b54c28ba8cc6ee7381fdf2ac.zip |
testsuite/synth: add testcase for #956
Diffstat (limited to 'testsuite/synth/issue956/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue956/ent.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue956/ent.vhdl b/testsuite/synth/issue956/ent.vhdl new file mode 100644 index 000000000..eadfa2443 --- /dev/null +++ b/testsuite/synth/issue956/ent.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + i : in bit; + o : out bit + ); +end; + +architecture a of ent is + signal test : std_logic_vector(0 to 7); +begin + process(i) + begin + for x in test'low to test'high loop + end loop; + + o <= i; + end process; +end; |