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authorTristan Gingold <tgingold@free.fr>2019-09-30 21:04:55 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-30 21:04:55 +0200
commitbb00cae25caff518b54c28ba8cc6ee7381fdf2ac (patch)
tree9f7afea27413c5f22105b932d471c3cc3c2e7109
parent21e59e89b5437ae0f3715b3f84f47f446e91d52d (diff)
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testsuite/synth: add testcase for #956
-rw-r--r--testsuite/synth/issue956/ent.vhdl21
-rwxr-xr-xtestsuite/synth/issue956/testsuite.sh11
2 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/synth/issue956/ent.vhdl b/testsuite/synth/issue956/ent.vhdl
new file mode 100644
index 000000000..eadfa2443
--- /dev/null
+++ b/testsuite/synth/issue956/ent.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+ port (
+ i : in bit;
+ o : out bit
+ );
+end;
+
+architecture a of ent is
+ signal test : std_logic_vector(0 to 7);
+begin
+ process(i)
+ begin
+ for x in test'low to test'high loop
+ end loop;
+
+ o <= i;
+ end process;
+end;
diff --git a/testsuite/synth/issue956/testsuite.sh b/testsuite/synth/issue956/testsuite.sh
new file mode 100755
index 000000000..54e687d28
--- /dev/null
+++ b/testsuite/synth/issue956/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for f in ent; do
+ synth $f.vhdl -e $f > syn_$f.vhdl
+# analyze syn_$f.vhdl
+done
+clean
+
+echo "Test successful"