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author | Tristan Gingold <tgingold@free.fr> | 2023-01-27 22:08:39 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-27 22:08:39 +0100 |
commit | 2efaa2396acf02fecc75341eb88353a325290e0b (patch) | |
tree | c6171b56b4b7ac40574dbec49ee1c9c02e2efc58 /testsuite/synth/issue2327/test_and.vhdl | |
parent | b878e8b41bafd21df4179a223f551236fc782707 (diff) | |
download | ghdl-2efaa2396acf02fecc75341eb88353a325290e0b.tar.gz ghdl-2efaa2396acf02fecc75341eb88353a325290e0b.tar.bz2 ghdl-2efaa2396acf02fecc75341eb88353a325290e0b.zip |
testsuite/synth: add tests for #2327
Diffstat (limited to 'testsuite/synth/issue2327/test_and.vhdl')
-rw-r--r-- | testsuite/synth/issue2327/test_and.vhdl | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/testsuite/synth/issue2327/test_and.vhdl b/testsuite/synth/issue2327/test_and.vhdl new file mode 100644 index 000000000..e6bd17449 --- /dev/null +++ b/testsuite/synth/issue2327/test_and.vhdl @@ -0,0 +1,11 @@ +entity test is + port( + a: in bit_vector(7 downto 0); + b: in bit; + c: out bit_vector(7 downto 0)); +end test; + +architecture behavior of test is +begin + c <= a and b; +end behavior; |