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author | Tristan Gingold <tgingold@free.fr> | 2022-07-11 07:34:14 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-07-11 07:34:14 +0200 |
commit | 02588566f171f87109d026f8fbbc39796eada17c (patch) | |
tree | daed7f0c6ebcceb12becb24e1d9cd75d153a9213 /testsuite/synth/issue2125/afed.vhdl | |
parent | 328aa863c6258c89e74ad04895dfc0484fe859e0 (diff) | |
download | ghdl-02588566f171f87109d026f8fbbc39796eada17c.tar.gz ghdl-02588566f171f87109d026f8fbbc39796eada17c.tar.bz2 ghdl-02588566f171f87109d026f8fbbc39796eada17c.zip |
testsuite/synth: add a test for #2125
Diffstat (limited to 'testsuite/synth/issue2125/afed.vhdl')
-rw-r--r-- | testsuite/synth/issue2125/afed.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/issue2125/afed.vhdl b/testsuite/synth/issue2125/afed.vhdl new file mode 100644 index 000000000..341545eb8 --- /dev/null +++ b/testsuite/synth/issue2125/afed.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity afed is + port ( + sig : in std_logic; + ack : in std_logic; + fe : out std_logic + ); +end entity; + +architecture behaviour of afed is + + signal fe_h : std_logic; + signal fe_l : std_logic; + +begin + + fe_h <= '0' when ack = '1' else + '1' when sig = '1'; + fe_l <= '0' when ack = '1' else + '1' when sig = '0' and fe_h = '1'; + + fe <= fe_l; + +end architecture; |