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authorTristan Gingold <tgingold@free.fr>2022-07-11 07:34:14 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-11 07:34:14 +0200
commit02588566f171f87109d026f8fbbc39796eada17c (patch)
treedaed7f0c6ebcceb12becb24e1d9cd75d153a9213 /testsuite/synth/issue2125/afed.vhdl
parent328aa863c6258c89e74ad04895dfc0484fe859e0 (diff)
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testsuite/synth: add a test for #2125
Diffstat (limited to 'testsuite/synth/issue2125/afed.vhdl')
-rw-r--r--testsuite/synth/issue2125/afed.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/issue2125/afed.vhdl b/testsuite/synth/issue2125/afed.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity afed is
+ port (
+ sig : in std_logic;
+ ack : in std_logic;
+ fe : out std_logic
+ );
+end entity;
+
+architecture behaviour of afed is
+
+ signal fe_h : std_logic;
+ signal fe_l : std_logic;
+
+begin
+
+ fe_h <= '0' when ack = '1' else
+ '1' when sig = '1';
+ fe_l <= '0' when ack = '1' else
+ '1' when sig = '0' and fe_h = '1';
+
+ fe <= fe_l;
+
+end architecture;