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author | Tristan Gingold <tgingold@free.fr> | 2022-07-05 06:32:49 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-07-05 06:32:49 +0200 |
commit | 811dbc83d990ea31f78a4775ffa7434298d4b5ae (patch) | |
tree | c69fd02853eac7200a85f4c1124488b994f23348 /testsuite/synth/issue2124/a.vhdl | |
parent | 16294762f5e521c6a159b7946794119615dc0b39 (diff) | |
download | ghdl-811dbc83d990ea31f78a4775ffa7434298d4b5ae.tar.gz ghdl-811dbc83d990ea31f78a4775ffa7434298d4b5ae.tar.bz2 ghdl-811dbc83d990ea31f78a4775ffa7434298d4b5ae.zip |
testsuite/synth: add a test for #2124
Diffstat (limited to 'testsuite/synth/issue2124/a.vhdl')
-rw-r--r-- | testsuite/synth/issue2124/a.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/issue2124/a.vhdl b/testsuite/synth/issue2124/a.vhdl new file mode 100644 index 000000000..ad35b843a --- /dev/null +++ b/testsuite/synth/issue2124/a.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity a is +end entity; + +architecture behaviour of a is + + component b + port ( + c : in std_logic; + q : out std_logic + ); + end component; + +begin + + inst : b + port map ( + c => '0', + q => open + ); + +end architecture; |