From 811dbc83d990ea31f78a4775ffa7434298d4b5ae Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 5 Jul 2022 06:32:49 +0200
Subject: testsuite/synth: add a test for #2124

---
 testsuite/synth/issue2124/a.vhdl | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 testsuite/synth/issue2124/a.vhdl

(limited to 'testsuite/synth/issue2124/a.vhdl')

diff --git a/testsuite/synth/issue2124/a.vhdl b/testsuite/synth/issue2124/a.vhdl
new file mode 100644
index 000000000..ad35b843a
--- /dev/null
+++ b/testsuite/synth/issue2124/a.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a is
+end entity;
+
+architecture behaviour of a is
+
+  component b
+    port (
+      c : in  std_logic;
+      q : out std_logic
+      );
+  end component;
+  
+begin
+
+  inst : b
+    port map (
+      c => '0',
+      q => open
+      );
+  
+end architecture;
-- 
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