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author | Tristan Gingold <tgingold@free.fr> | 2022-06-27 07:50:01 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-06-27 07:50:01 +0200 |
commit | e5e2caa620846928bb85ccc5206375c2b7321a66 (patch) | |
tree | 3341bfa45906c722efb33df4dc36f9a648e04278 /testsuite/synth/issue2109/bug.vhdl | |
parent | 928588eca00ad47ce0eee614c4f655ed109bf964 (diff) | |
download | ghdl-e5e2caa620846928bb85ccc5206375c2b7321a66.tar.gz ghdl-e5e2caa620846928bb85ccc5206375c2b7321a66.tar.bz2 ghdl-e5e2caa620846928bb85ccc5206375c2b7321a66.zip |
testsuite/synth: add a test for #2109
Diffstat (limited to 'testsuite/synth/issue2109/bug.vhdl')
-rw-r--r-- | testsuite/synth/issue2109/bug.vhdl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/synth/issue2109/bug.vhdl b/testsuite/synth/issue2109/bug.vhdl new file mode 100644 index 000000000..c514c6f99 --- /dev/null +++ b/testsuite/synth/issue2109/bug.vhdl @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is +generic( + tmp : std_ulogic_vector(0 downto 1) := "" +); +port( + val : out std_ulogic_vector(0 downto 1) +); +end entity; + +architecture rtl of bug is +begin + val <= tmp; +end architecture; |