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author | Tristan Gingold <tgingold@free.fr> | 2022-03-20 08:51:18 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-03-20 08:51:18 +0100 |
commit | 6058f2f6e79683e6b80b4974220a753373a8b411 (patch) | |
tree | 6c4a871bc6c6cc22edac6d7240fe907fa36485e7 /testsuite/synth/issue2013/tc3.vhdl | |
parent | 62337bdcb2260b82a5662aee9c8e661e05fb0faf (diff) | |
download | ghdl-6058f2f6e79683e6b80b4974220a753373a8b411.tar.gz ghdl-6058f2f6e79683e6b80b4974220a753373a8b411.tar.bz2 ghdl-6058f2f6e79683e6b80b4974220a753373a8b411.zip |
testsuite/synth: add a test for #2013
Diffstat (limited to 'testsuite/synth/issue2013/tc3.vhdl')
-rw-r--r-- | testsuite/synth/issue2013/tc3.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/issue2013/tc3.vhdl b/testsuite/synth/issue2013/tc3.vhdl new file mode 100644 index 000000000..da029fe9a --- /dev/null +++ b/testsuite/synth/issue2013/tc3.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tc3 is + port ( + state : in std_ulogic; + o : out std_ulogic_vector(3 downto 0) + ); +end entity tc3; + +architecture behaviour of tc3 is + signal misc_sel : std_ulogic_vector(3 downto 0); +begin + testcase_0: process(all) + begin + misc_sel <= "0000"; + + if state = '0' then + misc_sel <= "0111"; + else + misc_sel(3) <= '1'; + end if; + + o <= misc_sel; + end process; +end architecture behaviour; |