aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/synth/issue1945/alias02.vhdl
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2022-01-11 19:39:05 +0100
committerTristan Gingold <tgingold@free.fr>2022-01-12 08:30:18 +0100
commit4b97bbb1830f10ec17e07c5d312e35a83019a9ce (patch)
tree1fcf531958528e80bd6403b25a59c168aec87e83 /testsuite/synth/issue1945/alias02.vhdl
parent82bc056875df996138ffa54b89f52663dfb17f1a (diff)
downloadghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.tar.gz
ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.tar.bz2
ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.zip
testsuite/synth: add a test for #1945
Diffstat (limited to 'testsuite/synth/issue1945/alias02.vhdl')
-rw-r--r--testsuite/synth/issue1945/alias02.vhdl20
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/issue1945/alias02.vhdl b/testsuite/synth/issue1945/alias02.vhdl
new file mode 100644
index 000000000..010ed01c3
--- /dev/null
+++ b/testsuite/synth/issue1945/alias02.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+
+entity alias02 is
+ port(
+ i : in std_logic;
+ o : out std_logic_vector(7 downto 0)
+ );
+end entity;
+
+architecture rtl of alias02 is
+ alias o_alias : std_logic_vector(7 downto 2) is o(6 downto 1);
+ alias o_alias2 : std_logic_vector(3 downto 0) is o_alias(6 downto 3);
+begin
+ o (7) <= '1';
+ o (0) <= '1';
+ o_alias (7) <= '1';
+ o_alias (2) <= '1';
+ o_alias2 <= i & i & i & i;
+end architecture;