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author | Tristan Gingold <tgingold@free.fr> | 2021-09-08 18:08:36 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-09-08 18:08:36 +0200 |
commit | 054f40e6bd1e20f8f655d0a6beaf5789548ea030 (patch) | |
tree | 03e0455415a700c6aba8bd64e6d3723a372d018f /testsuite/synth/issue1856/detector.psl | |
parent | 604d6b287ec456f83826d7b2062876ad2298ebdc (diff) | |
download | ghdl-054f40e6bd1e20f8f655d0a6beaf5789548ea030.tar.gz ghdl-054f40e6bd1e20f8f655d0a6beaf5789548ea030.tar.bz2 ghdl-054f40e6bd1e20f8f655d0a6beaf5789548ea030.zip |
testsuite/synth: add a test for #1856
Diffstat (limited to 'testsuite/synth/issue1856/detector.psl')
-rw-r--r-- | testsuite/synth/issue1856/detector.psl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/synth/issue1856/detector.psl b/testsuite/synth/issue1856/detector.psl new file mode 100644 index 000000000..3b2ae4f76 --- /dev/null +++ b/testsuite/synth/issue1856/detector.psl @@ -0,0 +1,12 @@ +vunit i_rising_pulse_detector(rising_pulse_detector(rising_pulse_detector_1)) +{ + + default clock is rising_edge(clk); + + constant idx : natural := 4; + + --working cover without generate + fc_output_4 : cover {output_pulse(idx) = '1'}; + +} + |