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author | Tristan Gingold <tgingold@free.fr> | 2020-05-21 08:18:14 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-21 08:19:02 +0200 |
commit | 129c89c888ac617e875d012676c00782c2b1e8d4 (patch) | |
tree | 0132bc486c9f20fd7b589719aca18218c04c6a0e /testsuite/synth/issue1330/test.vhdl | |
parent | 9928dcea78c250b924cbe837c662dbeed4686376 (diff) | |
download | ghdl-129c89c888ac617e875d012676c00782c2b1e8d4.tar.gz ghdl-129c89c888ac617e875d012676c00782c2b1e8d4.tar.bz2 ghdl-129c89c888ac617e875d012676c00782c2b1e8d4.zip |
testsuite/synth: add tests for #1330
Diffstat (limited to 'testsuite/synth/issue1330/test.vhdl')
-rw-r--r-- | testsuite/synth/issue1330/test.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/issue1330/test.vhdl b/testsuite/synth/issue1330/test.vhdl new file mode 100644 index 000000000..7d2a17812 --- /dev/null +++ b/testsuite/synth/issue1330/test.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is + port( + clk : in std_logic; + write_data : in std_ulogic + ); +end entity test; + +architecture rtl of test is +begin + test_1: process(clk) + begin + if rising_edge(clk) then + assert write_data = '0' report "bad" severity failure; + end if; + end process test_1; +end architecture rtl; |