testsuite/synth: add tests for #1330

8 files changed, 189 insertions, 0 deletions

diff --git a/testsuite/synth/issue1330/tb_test.vhdl b/testsuite/synth/issue1330/tb_test.vhdl
new file mode 100644
index 000000000..6f1a714e6
--- /dev/null
+++ b/testsuite/synth/issue1330/tb_test.vhdl
@@ -0,0 +1,30 @@
+entity tb_test is
+end tb_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test is
+  signal clk : std_logic;
+  signal wr : std_logic;
+begin
+  dut: entity work.test
+    port map (clk, wr);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wr <= '0';
+    pulse;
+
+    pulse;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1330/tb_test2.vhdl b/testsuite/synth/issue1330/tb_test2.vhdl
new file mode 100644
index 000000000..84888fa96
--- /dev/null
+++ b/testsuite/synth/issue1330/tb_test2.vhdl
@@ -0,0 +1,37 @@
+entity tb_test2 is
+end tb_test2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test2 is
+  signal clk : std_logic;
+  signal wr : std_logic;
+  signal rst : std_logic;
+begin
+  dut: entity work.test2
+    port map (clk, wr, rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wr <= '0';
+    rst <= '1';
+    pulse;
+
+    rst <= '0';
+    pulse;
+
+    rst <= '1';
+    wr <= '1';
+    pulse;
+    
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1330/tb_test3.vhdl b/testsuite/synth/issue1330/tb_test3.vhdl
new file mode 100644
index 000000000..8710b807b
--- /dev/null
+++ b/testsuite/synth/issue1330/tb_test3.vhdl
@@ -0,0 +1,40 @@
+entity tb_test3 is
+end tb_test3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test3 is
+  signal clk : std_logic;
+  signal wr : std_logic;
+  signal arst : std_logic;
+begin
+  dut: entity work.test3
+    port map (clk, wr, arst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    wr <= '0';
+    arst <= '1';
+    pulse;
+
+    report "cycle 2";
+    arst <= '0';
+    pulse;
+
+    report "cycle 3";
+    
+    arst <= '1';
+    wr <= '1';
+    pulse;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1330/test.vhdl b/testsuite/synth/issue1330/test.vhdl
new file mode 100644
index 000000000..7d2a17812
--- /dev/null
+++ b/testsuite/synth/issue1330/test.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+    port(
+        clk : in std_logic;
+        write_data : in std_ulogic 
+        );
+end entity test;
+
+architecture rtl of test is
+begin
+    test_1: process(clk)
+    begin
+        if rising_edge(clk) then
+                assert write_data = '0' report "bad" severity failure;
+        end if;
+    end process test_1;
+end architecture rtl;
diff --git a/testsuite/synth/issue1330/test2.vhdl b/testsuite/synth/issue1330/test2.vhdl
new file mode 100644
index 000000000..928b638c7
--- /dev/null
+++ b/testsuite/synth/issue1330/test2.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2 is
+    port(
+        clk : in std_logic;
+        write_data : in std_ulogic;
+        rst : std_ulogic
+        );
+end;
+
+architecture rtl of test2 is
+begin
+    test_1: process(clk)
+    begin
+      if rising_edge(clk) then
+        if rst = '1' then
+          null;
+        else
+          assert write_data = '0' report "bad" severity failure;
+        end if;
+      end if;
+    end process test_1;
+end architecture rtl;
diff --git a/testsuite/synth/issue1330/test3.vhdl b/testsuite/synth/issue1330/test3.vhdl
new file mode 100644
index 000000000..a4216208e
--- /dev/null
+++ b/testsuite/synth/issue1330/test3.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test3 is
+    port(
+        clk : in std_logic;
+        write_data : in std_ulogic;
+        arst : std_ulogic
+        );
+end;
+
+architecture rtl of test3 is
+begin
+    test_1: process(clk, arst)
+    begin
+      if arst = '1' then
+        null;
+      elsif rising_edge(clk) then
+          assert write_data = '0' report "bad" severity failure;
+      end if;
+    end process test_1;
+end architecture rtl;
diff --git a/testsuite/synth/issue1330/testsuite.sh b/testsuite/synth/issue1330/testsuite.sh
new file mode 100755
index 000000000..557f33c9b
--- /dev/null
+++ b/testsuite/synth/issue1330/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb test
+synth_tb test2
+synth_tb test3
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1330/vassert.v b/testsuite/synth/issue1330/vassert.v
new file mode 100644
index 000000000..90e14f49f
--- /dev/null
+++ b/testsuite/synth/issue1330/vassert.v
@@ -0,0 +1,5 @@
+module vassert(input wire clk, input wire write);
+  always @(posedge clk)  begin
+     assert(write == 1'b0);
+  end
+endmodule