testsuite/synth: add tests for #1325

3 files changed, 47 insertions, 0 deletions

diff --git a/testsuite/synth/issue1325/rotate_testcase.vhdl b/testsuite/synth/issue1325/rotate_testcase.vhdl
new file mode 100644
index 000000000..594a805e4
--- /dev/null
+++ b/testsuite/synth/issue1325/rotate_testcase.vhdl
@@ -0,0 +1,15 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity rotate_testcase is
+    Port (in_vec:  in  UNSIGNED(31 downto 0);
+          out_vecl: out UNSIGNED(31 downto 0);
+          out_vecr: out UNSIGNED(31 downto 0));
+end entity;
+
+architecture RTL of rotate_testcase is
+begin
+    out_vecl <= rotate_left(in_vec,1);
+    out_vecr <= rotate_right(in_vec,1);
+end RTL;
diff --git a/testsuite/synth/issue1325/tb_rotate_testcase.vhdl b/testsuite/synth/issue1325/tb_rotate_testcase.vhdl
new file mode 100644
index 000000000..90f6ef910
--- /dev/null
+++ b/testsuite/synth/issue1325/tb_rotate_testcase.vhdl
@@ -0,0 +1,25 @@
+entity tb_rotate_testcase is
+end tb_rotate_testcase;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_Std.all;
+
+architecture behav of tb_rotate_testcase is
+  signal in_vec:  UNSIGNED(31 downto 0);
+  signal out_vecl: UNSIGNED(31 downto 0);
+  signal out_vecr:  UNSIGNED(31 downto 0);
+begin
+  dut: entity work.rotate_testcase
+    port map (in_vec, out_Vecl, out_vecr);
+
+  process
+  begin
+    in_vec <= x"1234_abcd";
+    wait for 1 ns;
+--    report to_hstring(out_vecr);
+    assert out_vecl = x"2469579a" severity failure;
+    assert out_vecr = x"891a55e6" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1325/testsuite.sh b/testsuite/synth/issue1325/testsuite.sh
new file mode 100755
index 000000000..20792b653
--- /dev/null
+++ b/testsuite/synth/issue1325/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb rotate_testcase
+
+echo "Test successful"