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-rw-r--r--testsuite/synth/issue1325/rotate_testcase.vhdl15
1 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/synth/issue1325/rotate_testcase.vhdl b/testsuite/synth/issue1325/rotate_testcase.vhdl
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+++ b/testsuite/synth/issue1325/rotate_testcase.vhdl
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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity rotate_testcase is
+ Port (in_vec: in UNSIGNED(31 downto 0);
+ out_vecl: out UNSIGNED(31 downto 0);
+ out_vecr: out UNSIGNED(31 downto 0));
+end entity;
+
+architecture RTL of rotate_testcase is
+begin
+ out_vecl <= rotate_left(in_vec,1);
+ out_vecr <= rotate_right(in_vec,1);
+end RTL;