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authorbwimm <be.wimm@gmail.com>2020-04-07 21:05:32 +0200
committerGitHub <noreply@github.com>2020-04-07 21:05:32 +0200
commit921e989f6e638cd655835040839b2c003385ec38 (patch)
tree5fc93437e27dd433733cb29de2045d51af5e6d62 /testsuite/synth/issue1179
parentdd36b3a7c22edeb73a821b1cd9f43c997920b3ef (diff)
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synth-static_oper: handle mul uns nat. (#1200)
Diffstat (limited to 'testsuite/synth/issue1179')
-rw-r--r--testsuite/synth/issue1179/bug.vhdl7
1 files changed, 5 insertions, 2 deletions
diff --git a/testsuite/synth/issue1179/bug.vhdl b/testsuite/synth/issue1179/bug.vhdl
index a4271b91f..70f7a8eca 100644
--- a/testsuite/synth/issue1179/bug.vhdl
+++ b/testsuite/synth/issue1179/bug.vhdl
@@ -4,7 +4,8 @@ use IEEE.numeric_std.all;
entity bug is
port(
- dummy : out positive
+ m0 : out positive;
+ m1 : out positive
);
end bug;
@@ -12,7 +13,9 @@ architecture behav of bug is
constant A : positive := 4;
constant B : positive := 1100;
constant C : positive := to_integer(A * to_unsigned(B, 11));
+ constant D : positive := to_integer(to_unsigned(B, 11) * A);
begin
- dummy <= c;
+ m0 <= c;
+ m1 <= d;
end architecture;