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authorTristan Gingold <tgingold@free.fr>2020-02-18 18:44:01 +0100
committerTristan Gingold <tgingold@free.fr>2020-02-18 18:44:01 +0100
commit3689e0eb1d8b4a9689afa6f76187f1ecdc5ec458 (patch)
tree77766bd7f22aaa0543872316060cc28a3cd66731 /testsuite/synth/issue1139/tb_ent.vhdl
parentd77dd8c6d657e447d3931d33c8ce5b637fbda758 (diff)
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testsuite/synth: add test for #1139
Diffstat (limited to 'testsuite/synth/issue1139/tb_ent.vhdl')
-rw-r--r--testsuite/synth/issue1139/tb_ent.vhdl28
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue1139/tb_ent.vhdl b/testsuite/synth/issue1139/tb_ent.vhdl
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+++ b/testsuite/synth/issue1139/tb_ent.vhdl
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+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+ signal a : std_logic;
+ signal b : std_logic;
+ signal z : std_logic;
+begin
+ dut: entity work.ent
+ port map (a, b, z);
+
+ process
+ constant av : std_logic_vector := b"1101";
+ constant bv : std_logic_vector := b"0111";
+ constant zv : std_logic_vector := b"0101";
+ begin
+ for i in av'range loop
+ a <= av (i);
+ b <= bv (i);
+ wait for 1 ns;
+ assert z = zv(i) severity failure;
+ end loop;
+ wait;
+ end process;
+end behav;