testsuite/synth: add test for #1139

4 files changed, 149 insertions, 0 deletions

diff --git a/testsuite/synth/issue1139/ent.vhdl b/testsuite/synth/issue1139/ent.vhdl
new file mode 100644
index 000000000..0bee9533d
--- /dev/null
+++ b/testsuite/synth/issue1139/ent.vhdl
@@ -0,0 +1,52 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity child is
+	port (
+		x : in std_logic;
+		y : out std_logic
+	);
+end;
+
+architecture a of child is
+begin
+	y <= x;
+end;
+
+-----------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+	port (
+		a : in std_logic;
+		b : in std_logic;
+		q : out std_logic
+	);
+end;
+
+architecture a of ent is
+	component child_comp is
+		port (
+			x : in std_logic;
+			y : out std_logic
+		);
+	end component;
+begin
+	child_inst: child_comp
+		port map (
+			x => a and b,
+			y => q
+		);
+end;
+
+-----------------------------------
+
+configuration conf of ent is
+	for a
+		for child_inst : child_comp
+			use entity work.child;
+		end for;
+	end for;
+end configuration;
diff --git a/testsuite/synth/issue1139/ent1.vhdl b/testsuite/synth/issue1139/ent1.vhdl
new file mode 100644
index 000000000..cb72d1ab0
--- /dev/null
+++ b/testsuite/synth/issue1139/ent1.vhdl
@@ -0,0 +1,52 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity child_1 is
+	port (
+		x : in std_logic;
+		y : out std_logic
+	);
+end;
+
+architecture a of child_1 is
+begin
+	y <= x;
+end;
+
+-----------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent_1 is
+	port (
+		a : in std_logic;
+		b : in std_logic;
+		q : out std_logic
+	);
+end;
+
+architecture a of ent_1 is
+	component child_comp is
+		port (
+			x : in std_logic;
+			y : out std_logic
+		);
+	end component;
+begin
+	child_inst: child_comp
+		port map (
+			x => a,
+			y => q
+		);
+end;
+
+-----------------------------------
+
+configuration conf_1 of ent_1 is
+	for a
+		for child_inst : child_comp
+			use entity work.child_1;
+		end for;
+	end for;
+end configuration;
diff --git a/testsuite/synth/issue1139/tb_ent.vhdl b/testsuite/synth/issue1139/tb_ent.vhdl
new file mode 100644
index 000000000..a8f3621ae
--- /dev/null
+++ b/testsuite/synth/issue1139/tb_ent.vhdl
@@ -0,0 +1,28 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+  signal a : std_logic;
+  signal b : std_logic;
+  signal z : std_logic;
+begin
+  dut: entity work.ent
+    port map (a, b, z);
+
+  process
+    constant av : std_logic_vector := b"1101";
+    constant bv : std_logic_vector := b"0111";
+    constant zv : std_logic_vector := b"0101";
+  begin
+    for i in av'range loop
+      a <= av (i);
+      b <= bv (i);
+      wait for 1 ns;
+      assert z = zv(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1139/testsuite.sh b/testsuite/synth/issue1139/testsuite.sh
new file mode 100755
index 000000000..f8a6ab35f
--- /dev/null
+++ b/testsuite/synth/issue1139/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate conf
+    clean
+
+    synth $t.vhdl -e conf > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"