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| author | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:15:29 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:15:29 +0100 |
| commit | 0416c788cd9aecd1a2bc8e7a517606d181d99921 (patch) | |
| tree | 4c3a8886cca8fb996f42118696e9369656018084 /testsuite/synth/issue1133 | |
| parent | c7d32abe6f8108c0e7af6eea5d546be2bd83b704 (diff) | |
| download | ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.tar.gz ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.tar.bz2 ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.zip | |
testsuite/synth: avoid use of verilog identifiers
Diffstat (limited to 'testsuite/synth/issue1133')
| -rw-r--r-- | testsuite/synth/issue1133/foo.vhdl | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/testsuite/synth/issue1133/foo.vhdl b/testsuite/synth/issue1133/foo.vhdl index 32a972cda..95dcddf55 100644 --- a/testsuite/synth/issue1133/foo.vhdl +++ b/testsuite/synth/issue1133/foo.vhdl @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; entity foo is port ( - input : in std_logic_vector(7 downto 0); + inp : in std_logic_vector(7 downto 0); output_ok : out std_logic_vector(7 downto 0); output_error : out std_logic_vector(7 downto 0) ); @@ -16,9 +16,9 @@ architecture foo of foo is begin -- This works fine - null_vector <= input(null_vector'range); + null_vector <= inp(null_vector'range); output_ok <= null_vector & (7 downto 0 => '0'); -- This doesn't - output_error <= input(-1 downto 0) & (7 downto 0 => '0'); + output_error <= inp(-1 downto 0) & (7 downto 0 => '0'); end foo; |