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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-30 10:25:21 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-30 10:25:21 +0100 |
| commit | 2bb61759d873dcffc8943f667073d472ca21a6dc (patch) | |
| tree | 350875aff9ea4376eccdff05eb159a2d248f75c1 /testsuite/synth/issue1044/ent.vhdl | |
| parent | 5b2d875da8d2c71f1dc5ab88c3fb4d6193afdb9f (diff) | |
| download | ghdl-2bb61759d873dcffc8943f667073d472ca21a6dc.tar.gz ghdl-2bb61759d873dcffc8943f667073d472ca21a6dc.tar.bz2 ghdl-2bb61759d873dcffc8943f667073d472ca21a6dc.zip | |
testsuite: add some tests for #1044
Diffstat (limited to 'testsuite/synth/issue1044/ent.vhdl')
| -rw-r--r-- | testsuite/synth/issue1044/ent.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/synth/issue1044/ent.vhdl b/testsuite/synth/issue1044/ent.vhdl new file mode 100644 index 000000000..fc98054d0 --- /dev/null +++ b/testsuite/synth/issue1044/ent.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + generic ( + VAL : real := 1.5 + ); + port ( + lt : out std_logic + ); +end; + +architecture a of ent is + constant fmul : real := val * 5.0; + constant fneg : real := -val; +begin + lt <= '1' when VAL < 1.5 else '0'; +end; + |