testsuite: add synth/fsm01

1 files changed, 44 insertions, 0 deletions

diff --git a/testsuite/synth/fsm01/tb_fsm_4s.vhdl b/testsuite/synth/fsm01/tb_fsm_4s.vhdl
new file mode 100644
index 000000000..ecd6b9da0
--- /dev/null
+++ b/testsuite/synth/fsm01/tb_fsm_4s.vhdl
@@ -0,0 +1,44 @@
+entity tb_fsm_4s is
+end tb_fsm_4s;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_fsm_4s is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal done : std_logic;
+begin
+  dut: entity work.fsm_4s
+    port map (
+      done => done,
+      d => din,
+      clk => clk,
+      rst => rst);
+
+  process
+    constant dat : std_logic_vector := b"1001_1001_1100";
+    constant res : std_logic_vector := b"0001_0001_0000";
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    din <= '0';
+    pulse;
+    assert done = '0' severity failure;
+    --  Test the whole sequence.
+    rst <= '0';
+    for i in dat'range loop
+      din <= dat (i);
+      pulse;
+      assert done = res(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;