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author | Tristan Gingold <tgingold@free.fr> | 2020-02-01 11:23:09 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-01 11:23:09 +0100 |
commit | 931ee6aa4161cecc46f0370623415116cf1a1d69 (patch) | |
tree | 7b00961856e83ea1483790ade4a6f3fbc27d8e57 /testsuite/synth/dff02/dff08c.vhdl | |
parent | 1fe0dce8f25255bcf9a3a3cfe317f763f1e410ce (diff) | |
download | ghdl-931ee6aa4161cecc46f0370623415116cf1a1d69.tar.gz ghdl-931ee6aa4161cecc46f0370623415116cf1a1d69.tar.bz2 ghdl-931ee6aa4161cecc46f0370623415116cf1a1d69.zip |
testsuite/synth: add more tests for #1122
Diffstat (limited to 'testsuite/synth/dff02/dff08c.vhdl')
-rw-r--r-- | testsuite/synth/dff02/dff08c.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/dff02/dff08c.vhdl b/testsuite/synth/dff02/dff08c.vhdl new file mode 100644 index 000000000..70626168c --- /dev/null +++ b/testsuite/synth/dff02/dff08c.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff08c is + port (q : out std_logic_vector(7 downto 0); + d : std_logic_vector(7 downto 0); + clk : std_logic; + en : std_logic; + rst : std_logic); +end dff08c; + +architecture behav of dff08c is + constant c : std_logic_vector(7 downto 0) := x"aa"; + signal p : std_logic_vector(7 downto 0) := c; +begin + process (clk, rst) is + begin + if en = '0' then + null; + elsif rst = '1' then + p <= c; + elsif rising_edge (clk) then + p <= d; + end if; + end process; + q <= p; +end behav; |