From 931ee6aa4161cecc46f0370623415116cf1a1d69 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 1 Feb 2020 11:23:09 +0100
Subject: testsuite/synth: add more tests for #1122

---
 testsuite/synth/dff02/dff08c.vhdl | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 testsuite/synth/dff02/dff08c.vhdl

(limited to 'testsuite/synth/dff02/dff08c.vhdl')

diff --git a/testsuite/synth/dff02/dff08c.vhdl b/testsuite/synth/dff02/dff08c.vhdl
new file mode 100644
index 000000000..70626168c
--- /dev/null
+++ b/testsuite/synth/dff02/dff08c.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08c is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        en : std_logic;
+        rst : std_logic);
+end dff08c;
+
+architecture behav of dff08c is
+  constant c : std_logic_vector(7 downto 0) := x"aa";
+  signal p : std_logic_vector(7 downto 0) := c;
+begin
+  process (clk, rst) is
+  begin
+    if en = '0' then
+      null;
+    elsif rst = '1' then
+      p <= c;
+    elsif rising_edge (clk) then
+      p <= d;
+    end if;
+  end process;
+  q <= p;
+end behav;
-- 
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