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author | Tristan Gingold <tgingold@free.fr> | 2019-10-15 06:04:03 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-15 06:04:03 +0200 |
commit | 2485c247d5eae5f88c37708c2346c015caf22dbc (patch) | |
tree | 4e9c4355c6509986689996390ba028249dc2aae8 /testsuite/synth/dff02/dff05.vhdl | |
parent | 9800901df71f3823b6bd8edd5a8548a0c8ab5098 (diff) | |
download | ghdl-2485c247d5eae5f88c37708c2346c015caf22dbc.tar.gz ghdl-2485c247d5eae5f88c37708c2346c015caf22dbc.tar.bz2 ghdl-2485c247d5eae5f88c37708c2346c015caf22dbc.zip |
testsuite/synth: add a test.
Diffstat (limited to 'testsuite/synth/dff02/dff05.vhdl')
-rw-r--r-- | testsuite/synth/dff02/dff05.vhdl | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/dff02/dff05.vhdl b/testsuite/synth/dff02/dff05.vhdl new file mode 100644 index 000000000..0a4f5d567 --- /dev/null +++ b/testsuite/synth/dff02/dff05.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff05 is + port (q : out std_logic_vector(7 downto 0); + d : std_logic_vector(7 downto 0); + clk : std_logic); +end dff05; + +architecture behav of dff05 is +begin + process (clk) is + begin + if rising_edge (clk) then + if d (7) = '1' then + q (0) <= d (0); + else + q (2) <= d (2); + end if; + end if; + end process; +end behav; |