testsuite/synth: add a test.

3 files changed, 68 insertions, 1 deletions

diff --git a/testsuite/synth/dff02/dff05.vhdl b/testsuite/synth/dff02/dff05.vhdl
new file mode 100644
index 000000000..0a4f5d567
--- /dev/null
+++ b/testsuite/synth/dff02/dff05.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff05 is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic);
+end dff05;
+
+architecture behav of dff05 is
+begin
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      if d (7) = '1' then
+        q (0) <= d (0);
+      else
+        q (2) <= d (2);
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/tb_dff05.vhdl b/testsuite/synth/dff02/tb_dff05.vhdl
new file mode 100644
index 000000000..00e7fec37
--- /dev/null
+++ b/testsuite/synth/dff02/tb_dff05.vhdl
@@ -0,0 +1,45 @@
+entity tb_dff05 is
+end tb_dff05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dff05 is
+  signal clk : std_logic;
+  signal din : std_logic_vector (7 downto 0);
+  signal dout : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.dff05
+    port map (
+      q => dout,
+      d => din,
+      clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= b"1_00000_00";
+    pulse;
+    assert dout (0) = '0' severity failure;
+
+    din <= b"0_00001_00";
+    pulse;
+    assert dout (2) = '1' severity failure;
+
+    din <= b"0_00000_01";
+    pulse;
+    assert dout (2) = '0' severity failure;
+
+    din <= b"1_00000_01";
+    pulse;
+    assert dout (0) = '1' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/dff02/testsuite.sh b/testsuite/synth/dff02/testsuite.sh
index 46be7defd..a479311ea 100755
--- a/testsuite/synth/dff02/testsuite.sh
+++ b/testsuite/synth/dff02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dff06 dff08; do
+for t in dff05 dff06 dff08; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean