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author | Tristan Gingold <tgingold@free.fr> | 2019-04-16 19:03:15 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-04-16 19:03:15 +0200 |
commit | 5336f2f3fb7f43ec208f1357588195fc2d915637 (patch) | |
tree | 6acf49a00abac08d651817167841c96981c84653 /testsuite/synth/dff01/dff01.vhdl | |
parent | bbbf1969105775e658d8d91c99b30f3934cb7275 (diff) | |
download | ghdl-5336f2f3fb7f43ec208f1357588195fc2d915637.tar.gz ghdl-5336f2f3fb7f43ec208f1357588195fc2d915637.tar.bz2 ghdl-5336f2f3fb7f43ec208f1357588195fc2d915637.zip |
testsuite: add dff01 tests.
Diffstat (limited to 'testsuite/synth/dff01/dff01.vhdl')
-rw-r--r-- | testsuite/synth/dff01/dff01.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/dff01/dff01.vhdl b/testsuite/synth/dff01/dff01.vhdl new file mode 100644 index 000000000..feb9fac3f --- /dev/null +++ b/testsuite/synth/dff01/dff01.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff01 is + port (q : out std_logic; + d : std_logic; + clk : std_logic); +end dff01; + +architecture behav of dff01 is +begin + process (clk) is + begin + if rising_edge (clk) then + q <= d; + end if; + end process; +end behav; |