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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-06 17:44:25 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-06 17:53:24 +0200 |
| commit | be9cdfbbe25b64ee587ba3316898fcc988830c0a (patch) | |
| tree | 8d0dbb580abb0dda2d9ec260bcf3bdf5b715785b /testsuite/synth/comp02/pkg.vhdl | |
| parent | 74348ad90435e6a28a86c4050d17a989f5434e9d (diff) | |
| download | ghdl-be9cdfbbe25b64ee587ba3316898fcc988830c0a.tar.gz ghdl-be9cdfbbe25b64ee587ba3316898fcc988830c0a.tar.bz2 ghdl-be9cdfbbe25b64ee587ba3316898fcc988830c0a.zip | |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/comp02/pkg.vhdl')
| -rw-r--r-- | testsuite/synth/comp02/pkg.vhdl | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/testsuite/synth/comp02/pkg.vhdl b/testsuite/synth/comp02/pkg.vhdl new file mode 100644 index 000000000..8d834a280 --- /dev/null +++ b/testsuite/synth/comp02/pkg.vhdl @@ -0,0 +1,11 @@ +library ieee; +use ieee.std_logic_1164.all; + +package pkg is + component cmask is + generic + (mask : std_logic_vector (0 to 7)); + port (d : std_logic_vector (7 downto 0); + o : out std_logic_vector (7 downto 0)); + end component; +end pkg; |