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authorTristan Gingold <tgingold@free.fr>2020-05-09 11:02:23 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-09 11:22:01 +0200
commit1a65ac6bbbaf6cdaf1ea93c0c46f2e97e12e9dcc (patch)
tree13d03fcaf314a19649f4ed1c750d8f01678a027e /testsuite/synth/case01/case03.vhdl
parentb13b9e9fa26121a68d74589ef35ea5ed45316cd9 (diff)
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testsuite/synth: add case tests for corner case.
Diffstat (limited to 'testsuite/synth/case01/case03.vhdl')
-rw-r--r--testsuite/synth/case01/case03.vhdl13
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/case01/case03.vhdl b/testsuite/synth/case01/case03.vhdl
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+++ b/testsuite/synth/case01/case03.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity case03 is
+ port (a : std_logic_vector (4 downto 0);
+ o : out std_logic);
+end case03;
+
+architecture behav of case03 is
+begin
+ with a select o <=
+ '0' when others;
+end behav;