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authorTristan Gingold <tgingold@free.fr>2022-09-12 05:11:58 +0200
committerTristan Gingold <tgingold@free.fr>2022-09-12 05:11:58 +0200
commit904abc55c0821f85151a8328904f5621e60c8f02 (patch)
tree7fa4aeb46d0a35384ecd0bc4fbe001b6d6ea6833 /testsuite/synth/attr02/tb_succ01.vhdl
parent59c75d5b5bbb819e164402d1b023b8090261818b (diff)
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testsuite/synth: add tests for succ/pred/leftof/rightof attributes
Diffstat (limited to 'testsuite/synth/attr02/tb_succ01.vhdl')
-rw-r--r--testsuite/synth/attr02/tb_succ01.vhdl17
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/synth/attr02/tb_succ01.vhdl b/testsuite/synth/attr02/tb_succ01.vhdl
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index 000000000..8ff2d31dc
--- /dev/null
+++ b/testsuite/synth/attr02/tb_succ01.vhdl
@@ -0,0 +1,17 @@
+entity tb_succ01 is
+end tb_succ01;
+
+architecture behav of tb_succ01 is
+ signal i, o : integer;
+begin
+ dut: entity work.succ01
+ port map (i, o);
+
+ process
+ begin
+ i <= 5;
+ wait for 1 ns;
+ assert o = 6 severity failure;
+ wait;
+ end process;
+end behav;