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author | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:56:54 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:56:54 +0200 |
commit | 8a6f0ea2e97693dcefecfb29697f835729ead164 (patch) | |
tree | 97085b2f1fb37bfbd46e5accf9801e569e7a2b05 /testsuite/synth/arr02/dpram1.vhdl | |
parent | e32547e4d3a58aab91ffdc4d770a0b7f4d417fc9 (diff) | |
download | ghdl-8a6f0ea2e97693dcefecfb29697f835729ead164.tar.gz ghdl-8a6f0ea2e97693dcefecfb29697f835729ead164.tar.bz2 ghdl-8a6f0ea2e97693dcefecfb29697f835729ead164.zip |
synth: add a test for a ram.
Diffstat (limited to 'testsuite/synth/arr02/dpram1.vhdl')
-rw-r--r-- | testsuite/synth/arr02/dpram1.vhdl | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/arr02/dpram1.vhdl b/testsuite/synth/arr02/dpram1.vhdl new file mode 100644 index 000000000..ca1cf724a --- /dev/null +++ b/testsuite/synth/arr02/dpram1.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dpram1 is + port (raddr : std_logic_vector (3 downto 0); + rdat : out std_logic_vector (7 downto 0); + waddr : std_logic_vector (3 downto 0); + wdat : std_logic_vector (7 downto 0); + clk : std_logic); +end dpram1; + +architecture behav of dpram1 is + type memtype is array (15 downto 0) of std_logic_vector (7 downto 0); + signal mem : memtype; +begin + process (clk) + begin + if rising_edge (clk) then + rdat <= mem (to_integer(unsigned (raddr))); + mem (to_integer(unsigned (waddr))) <= wdat; + end if; + end process; +end behav; |