Improved VHDL example project.

8 files changed, 77 insertions, 62 deletions

diff --git a/testsuite/pyunit/dom/StopWatch.py b/testsuite/pyunit/dom/StopWatch.py
index b733cd786..6301eb1df 100644
--- a/testsuite/pyunit/dom/StopWatch.py
+++ b/testsuite/pyunit/dom/StopWatch.py
@@ -60,13 +60,16 @@ class Designs(TestCase):
         ("lib_StopWatch", Path("Counter.vhdl")),
         ("lib_StopWatch", Path("seg7_Encoder.vhdl")),
         ("lib_StopWatch", Path("seg7_Display.vhdl")),
+        ("lib_StopWatch", Path("seg7_Display.cfg.vhdl")),
         ("lib_StopWatch", Path("toplevel.Display.vhdl")),
     )
     _stopwatchFiles = _packageFiles + (
         ("lib_Utilities", Path("Counter.vhdl")),
         ("lib_StopWatch", Path("seg7_Encoder.vhdl")),
         ("lib_StopWatch", Path("seg7_Display.vhdl")),
+        ("lib_StopWatch", Path("seg7_Display.cfg.vhdl")),
         ("lib_StopWatch", Path("StopWatch.vhdl")),
+        ("lib_Utilities", Path("sync_Bits.vhdl")),
         ("lib_Utilities", Path("Debouncer.vhdl")),
         ("lib_StopWatch", Path("toplevel.StopWatch.vhdl")),
     )
diff --git a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl
index 4e687da0b..ef1474164 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl
@@ -15,7 +15,8 @@ entity Debouncer is
 		CLOCK_PERIOD   : time := 10 ns;
 		DEBOUNCE_TIME  : time := 3 ms;
 
-		BITS           : positive
+		BITS           : positive;
+		INPUT_SYNC     : boolean := true
 	);
 	port (
 		Clock  : in  std_logic;
@@ -29,12 +30,27 @@ architecture rtl of Debouncer is
 	constant DEBOUNCE_COUNTER_MAX  : positive := DEBOUNCE_TIME / (CLOCK_PERIOD* ite(IS_SIMULATION, 20, 1));
 	constant DEBOUNCE_COUNTER_BITS : positive := log2(DEBOUNCE_COUNTER_MAX);
 
+	signal Input_sync : Input'subtype;
 begin
 	assert false report "CLOCK_PERIOD:         " & time'image(CLOCK_PERIOD);
 	assert false report "DEBOUNCE_TIME:        " & time'image(DEBOUNCE_TIME);
 	--assert false report "DEBOUNCE_COUNTER_MAX: " & to_string(10 ns);
 	--assert false report "INTEGER'high:         " & integer'image(integer'high);
 
+	genSync: if INPUT_SYNC generate
+		sync: entity work.sync_Bits
+			generic map (
+				BITS => BITS
+			)
+			port map (
+				Clock  => Clock,
+				Input  => Input,
+				Output => Input_sync
+			);
+	else generate
+		Input_sync <= Input;
+	end generate;
+
 	genBits: for i in Input'range generate
 		signal DebounceCounter         : signed(DEBOUNCE_COUNTER_BITS downto 0) := to_signed(DEBOUNCE_COUNTER_MAX - 3, DEBOUNCE_COUNTER_BITS + 1);
 	begin
diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
index 1a40718aa..f67f99c72 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl
@@ -18,4 +18,16 @@ package StopWatch_pkg is
 	end record;
 
 	type T_STOPWATCH_CONFIGURATION is array(natural range <>) of T_DIGIT_CONFIGURATION;
+
+	-- Encoder that translates from 4-bit binary (BCD) to 7-segment code.
+	--
+	-- In addition, an optional dot input is supported.
+	component seg7_Encoder is
+		port (
+			BCDValue  : in  T_BCD;
+			Dot       : in  std_logic  := '0';
+
+			Seg7Code  : out std_logic_vector(7 downto 0)
+		);
+	end component;
 end package;
diff --git a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl
index e15048dcf..6231261c0 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/Utilities.pkg.vhdl
@@ -30,6 +30,21 @@ package Utilities_pkg is
 
 	function to_index(value : unsigned; max : positive) return natural;
 	function to_index(value : natural;  max : positive) return natural;
+
+	component Debouncer is
+		generic (
+			CLOCK_PERIOD   : time := 10 ns;
+			DEBOUNCE_TIME  : time := 3 ms;
+
+			BITS           : positive
+		);
+		port (
+			Clock  : in  std_logic;
+
+			Input  : in  std_logic_vector(BITS - 1 downto 0);
+			Output : out std_logic_vector(BITS - 1 downto 0) := (others => '0')
+		);
+	end component;
 end package;
 
 
diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl
index 88074c884..63d0c5e60 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.cfg.vhdl
@@ -7,36 +7,10 @@ context work.StopWatch_ctx;
 
 
 -- Encoder that translates from 4-bit binary (BCD) to 7-segment code.
-entity seg7_Encoder is
-	port (
-		BCDValue  : in  T_BCD;
-		Dot       : in  std_logic  := '0';
-
-		Seg7Code  : out std_logic_vector(7 downto 0)
-	);
-end entity;
-
-
-architecture rtl of seg7_Encoder is
-
-begin
-	process(BCDValue, Dot)
-		variable temp : std_logic_vector(6 downto 0);
-	begin
-		case BCDValue is -- segments:  GFEDCBA     -- Segment Pos.   Index Pos.
-			when x"0" =>        temp := "0111111";   --
-			when x"1" =>        temp := "0000110";   --
-			when x"2" =>        temp := "1011011";   -- 	 AAA           000
-			when x"3" =>        temp := "1001111";   -- 	F   B         5   1
-			when x"4" =>        temp := "1100110";   -- 	F   B         5   1
-			when x"5" =>        temp := "1101101";   -- 	 GGG           666
-			when x"6" =>        temp := "1111101";   -- 	E   C         4   2
-			when x"7" =>        temp := "0000111";   -- 	E   C         4   2
-			when x"8" =>        temp := "1111111";   -- 	 DDD  DOT      333  7
-			when x"9" =>        temp := "1101111";   --
-			when others =>      temp := "XXXXXXX";   --
-		end case;
-
-		Seg7Code <= Dot & temp;
-	end process;
-end architecture;
+configuration seg7_Display_cfg of seg7_Display is
+	for rtl
+		for enc : seg7_Encoder
+			use entity work.seg7_Encoder(rtl);
+		end for;
+	end for;
+end configuration;
diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl
index 12e8e55aa..da21075cf 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl
@@ -79,7 +79,7 @@ begin
 	Dot   <= DotValues(to_index(Digit_Select, DotValues'high));
 
 	-- 7-segment encoder
-	enc: entity work.seg7_Encoder
+	enc: configuration seg7_Encoder
 		port map (
 			BCDValue  => Digit,
 			Dot       => Dot,
diff --git a/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl
index 88074c884..499305ec7 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/sync_Bits.vhdl
@@ -1,42 +1,37 @@
 -- Author:  Patrick Lehmann
 -- License: MIT
 --
--- A generic counter module used in the StopWatch example.
+-- A generic multi-FF synchronizer.
 --
-context work.StopWatch_ctx;
+library ieee;
+use     ieee.std_logic_1164.all;
 
 
--- Encoder that translates from 4-bit binary (BCD) to 7-segment code.
-entity seg7_Encoder is
+-- Multi-stage FF synchronizer
+entity sync_Bits is
+	generic (
+		BITS      : positive              := 1;
+		STAGES    : positive range 2 to 5 := 3
+	);
 	port (
-		BCDValue  : in  T_BCD;
-		Dot       : in  std_logic  := '0';
+		Clock     : in  std_logic;
 
-		Seg7Code  : out std_logic_vector(7 downto 0)
+		Input     : in  std_logic_vector(BITS - 1 downto 0);
+		output    : in  std_logic_vector(BITS - 1 downto 0)
 	);
 end entity;
 
 
-architecture rtl of seg7_Encoder is
+architecture rtl of sync_Bits is
 
 begin
-	process(BCDValue, Dot)
-		variable temp : std_logic_vector(6 downto 0);
+	gen : for i in Input'range generate
+		signal meta   : std_logic := '0';
+		signal ffs    : std_logic_vector(STAGES - 1 downto 1) := (others => '0');
 	begin
-		case BCDValue is -- segments:  GFEDCBA     -- Segment Pos.   Index Pos.
-			when x"0" =>        temp := "0111111";   --
-			when x"1" =>        temp := "0000110";   --
-			when x"2" =>        temp := "1011011";   -- 	 AAA           000
-			when x"3" =>        temp := "1001111";   -- 	F   B         5   1
-			when x"4" =>        temp := "1100110";   -- 	F   B         5   1
-			when x"5" =>        temp := "1101101";   -- 	 GGG           666
-			when x"6" =>        temp := "1111101";   -- 	E   C         4   2
-			when x"7" =>        temp := "0000111";   -- 	E   C         4   2
-			when x"8" =>        temp := "1111111";   -- 	 DDD  DOT      333  7
-			when x"9" =>        temp := "1101111";   --
-			when others =>      temp := "XXXXXXX";   --
-		end case;
+		meta      <= Input(i) when rising_edge(Clock);
+		ffs       <= (ffs(ffs'left downto 1) & meta) when rising_edge(Clock);
 
-		Seg7Code <= Dot & temp;
-	end process;
+		Output(i) <= ffs(ffs'left);
+	end generate;
 end architecture;
diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl
index 7bb6e9cd9..08046e2cc 100644
--- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl
+++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl
@@ -59,7 +59,7 @@ begin
 	Board_Reset <= not NexysA7_GPIO_Button_Reset_n;
 
 	-- Debounce input signals
-	deb: entity work.Debouncer
+	deb: component Debouncer
 		generic map (
 			CLOCK_PERIOD  => CLOCK_PERIOD,
 			BITS          => 2
@@ -100,7 +100,7 @@ begin
 		);
 
 	-- 7-segment display
-	display: entity work.seg7_Display
+	display: configuration seg7_Display_cfg
 		generic map (
 			CLOCK_PERIOD  => CLOCK_PERIOD,
 			DIGITS        => Digits'length