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author | Tristan Gingold <tgingold@free.fr> | 2019-08-11 05:11:17 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-08-11 05:11:17 +0200 |
commit | 184c2eb7f97f412ab6d658271ecacd7b6cae1837 (patch) | |
tree | 58c83ad0d872d6fd08b5b80fae6562cca8fd6190 /testsuite/gna | |
parent | dfae8e99b73ba3cf10c7aa95d88ba380946ecef7 (diff) | |
download | ghdl-184c2eb7f97f412ab6d658271ecacd7b6cae1837.tar.gz ghdl-184c2eb7f97f412ab6d658271ecacd7b6cae1837.tar.bz2 ghdl-184c2eb7f97f412ab6d658271ecacd7b6cae1837.zip |
Add testcase for #885
Diffstat (limited to 'testsuite/gna')
-rw-r--r-- | testsuite/gna/issue885/a.vhdl | 33 | ||||
-rwxr-xr-x | testsuite/gna/issue885/testsuite.sh | 11 |
2 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/gna/issue885/a.vhdl b/testsuite/gna/issue885/a.vhdl new file mode 100644 index 000000000..331500a4d --- /dev/null +++ b/testsuite/gna/issue885/a.vhdl @@ -0,0 +1,33 @@ +entity ent is +end entity; + +library ieee; +use ieee.std_logic_1164.all; +package avmm_csr_pkg is + type avmm_csr_array_t is array (natural range <>) of std_logic_vector(31 downto 0); +end avmm_csr_pkg; + + +library ieee; +use work.avmm_csr_pkg.all; +entity avmm_csr is + Port ( + reg_i : in avmm_csr_array_t + ); +end avmm_csr; +architecture rtl of avmm_csr is +begin +end rtl; + +library ieee; +use ieee.numeric_std_unsigned.all; +entity dut is +end entity dut; +architecture rtl of dut is + signal int : natural; +begin + inst : entity work.avmm_csr + port map ( + reg_i(0) => to_slv(int, 32) + ); +end architecture rtl; diff --git a/testsuite/gna/issue885/testsuite.sh b/testsuite/gna/issue885/testsuite.sh new file mode 100755 index 000000000..f2257212f --- /dev/null +++ b/testsuite/gna/issue885/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze a.vhdl +elab_simulate dut + +clean + +echo "Test successful" |