From 184c2eb7f97f412ab6d658271ecacd7b6cae1837 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 11 Aug 2019 05:11:17 +0200
Subject: Add testcase for #885

---
 testsuite/gna/issue885/a.vhdl       | 33 +++++++++++++++++++++++++++++++++
 testsuite/gna/issue885/testsuite.sh | 11 +++++++++++
 2 files changed, 44 insertions(+)
 create mode 100644 testsuite/gna/issue885/a.vhdl
 create mode 100755 testsuite/gna/issue885/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue885/a.vhdl b/testsuite/gna/issue885/a.vhdl
new file mode 100644
index 000000000..331500a4d
--- /dev/null
+++ b/testsuite/gna/issue885/a.vhdl
@@ -0,0 +1,33 @@
+entity ent is
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+package avmm_csr_pkg is
+   type avmm_csr_array_t is array (natural range <>) of std_logic_vector(31 downto 0);
+end avmm_csr_pkg;
+
+
+library ieee;
+use work.avmm_csr_pkg.all;
+entity avmm_csr is
+	Port (
+		reg_i : in avmm_csr_array_t
+    );
+end avmm_csr;
+architecture rtl of avmm_csr is
+begin
+end rtl;
+
+library ieee;
+use ieee.numeric_std_unsigned.all;
+entity dut is
+end entity dut;
+architecture rtl of dut is
+    signal int : natural;
+begin
+    inst : entity work.avmm_csr
+    port map (
+        reg_i(0)           => to_slv(int, 32)
+    );
+end architecture rtl;
diff --git a/testsuite/gna/issue885/testsuite.sh b/testsuite/gna/issue885/testsuite.sh
new file mode 100755
index 000000000..f2257212f
--- /dev/null
+++ b/testsuite/gna/issue885/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze a.vhdl
+elab_simulate dut
+
+clean
+
+echo "Test successful"
-- 
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