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author | Tristan Gingold <tgingold@free.fr> | 2022-11-08 18:40:32 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-11-08 18:42:50 +0100 |
commit | 0abcfa29b88342d471c5baf0a140d65be0979ac9 (patch) | |
tree | 70d778280896a84b1b7372b49ea046f2792b7e8d /testsuite/gna | |
parent | 6f76368d49f445299691cb9013e03216188fc34c (diff) | |
download | ghdl-0abcfa29b88342d471c5baf0a140d65be0979ac9.tar.gz ghdl-0abcfa29b88342d471c5baf0a140d65be0979ac9.tar.bz2 ghdl-0abcfa29b88342d471c5baf0a140d65be0979ac9.zip |
testsuite/gna: add a test for #2239
Diffstat (limited to 'testsuite/gna')
-rw-r--r-- | testsuite/gna/issue2239/ent.vhdl | 25 | ||||
-rwxr-xr-x | testsuite/gna/issue2239/testsuite.sh | 9 |
2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/gna/issue2239/ent.vhdl b/testsuite/gna/issue2239/ent.vhdl new file mode 100644 index 000000000..bc7b93998 --- /dev/null +++ b/testsuite/gna/issue2239/ent.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end entity; + +architecture behaviour of ent is + + signal test : std_logic_vector(3 downto 0); + + procedure DUMMY (signal slv : out std_logic_vector(7 downto 0)) is + begin + slv <= x"00"; + end procedure; + +begin + + process + begin + DUMMY (slv(7 downto 4) => open, + slv(3 downto 0) => test); + wait; + end process; + +end architecture; diff --git a/testsuite/gna/issue2239/testsuite.sh b/testsuite/gna/issue2239/testsuite.sh new file mode 100755 index 000000000..9e7e2a886 --- /dev/null +++ b/testsuite/gna/issue2239/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure ent.vhdl + +clean + +echo "Test successful" |