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author | Tristan Gingold <tgingold@free.fr> | 2017-12-08 06:56:55 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-12-08 06:56:55 +0100 |
commit | 7c1a8746d2b4fc076bcb287c8917af750a6b3d58 (patch) | |
tree | bb55692015e91a185370bcda0e4f1439c4f2d137 /testsuite/gna/issue478/repro.vhdl | |
parent | 151a1afff5c36a4681820a704cf60922d26df5b5 (diff) | |
download | ghdl-7c1a8746d2b4fc076bcb287c8917af750a6b3d58.tar.gz ghdl-7c1a8746d2b4fc076bcb287c8917af750a6b3d58.tar.bz2 ghdl-7c1a8746d2b4fc076bcb287c8917af750a6b3d58.zip |
Add testcase for #478
Diffstat (limited to 'testsuite/gna/issue478/repro.vhdl')
-rw-r--r-- | testsuite/gna/issue478/repro.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/gna/issue478/repro.vhdl b/testsuite/gna/issue478/repro.vhdl new file mode 100644 index 000000000..e0a424ae7 --- /dev/null +++ b/testsuite/gna/issue478/repro.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity EX_ALUControl is +end entity; + +architecture foo of EX_ALUControl is + signal RST: std_logic; + signal RDY: std_logic; + signal reentry_guard: std_logic; +begin + +NO_LABEL: + process (RST, RDY, reentry_guard) + begin + report "In EX_ALUControl (RST=" & Std_logic'image(RST) & ", RDY=" & + Std_logic'image(RDY) & ", re=" & + Std_logic'image(reentry_guard) ")"; -- MISSING AMPERSAND + end process; +end architecture; |